A programmable logic device, such as field programmable gate array (FPGA) or a complex programmable logic device (CPLD), may be used in a variety of applications. A programmable logic device (PLD) offers the advantage of being reprogrammable in the field (e.g., while on the circuit board in its operational environment) to provide a wide range of programmable functions. A PLD may also provide certain advantages for implementing new product designs in integrated circuits relative to other traditional technologies (e.g., an application specific integrated circuit (ASIC) or an application specific standard product (ASSP)), such as for example, in terms of non-recurring engineering costs and other product development costs.
A conventional PLD typically supports the IEEE 1149.1 boundary scan test interface standard (also known as the JTAG standard) and therefore, for example, may be implemented as part of a JTAG scan chain. However, a drawback of a conventional PLD is that a user of the PLD cannot change the PLD's hard-wired 32-bit boundary scan identification code (IDCODE), which includes information regarding the manufacturer of the PLD along with device and version information. For example, a user of the PLD may want to change the identification code of the PLD so that the PLD will appear as the user's custom or proprietary device (e.g., the user's ASSP within the JTAG scan chain). As a result, there is a need for improved techniques directed towards PLD identification codes.